Agilent/HP E2411C 486 Preprocessor Interface

Agilent/HP E2411C 486 Preprocessor Interface
Manufacturer: Agilent / HP
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Agilent/HP E2411C Preprocessor Interface

 

Agilent/HP E2411C Preprocessor Interface

    The Agilent/HP E2411C analysis probe (formerly known as a preprocessor interface) supports the Intel i486DX, DX2, DX4, i486SX, i486SL Enhanced, i487SX, as well as the OverDrive for the i486DX. The probe provides an electrical and mechanical connection between your target system and an HP logic analyzer or logic analysis system.

Features
  • Quick configuration of the logic analyzer with address, data and status signals for the Intel 486 processor
  • Support for state and timing analysis
  • Intel 80486 mnemonics in the trace listing for easy correlation with captured data
  • FPU instructions decoded in the display
  • Filters and color coding to show and/or suppress different types of instructions

   The Agilent/HP E2411C preprocessor supports the Intel486DX, DX2, DX4, 486SX, 486SL Enhanced, and 487SX, as well as the OverDrive for the 486DX chip. The preprocessor interface provides an electrical and mechanical connection between your target system and an HP logic analyzer. Preprocessor software configures the logic analyzer labeling address, data, and status lines. Additionally, when a state trace is displayed, the data is disassembled and listed in 80486 mnemonics. The disassembler also decodes FPU instructions for target systems that use the Intel486DX and Intel487SX chips.

Supply Voltage

   The AgilentHP E2411C supports both 3.3V and 5V versions of the Intel486 family of processors.

Capabilities

   State per clock modeprovides a complete display of all bus activity, including wait states, idle states, and cache invalidation cycles. State per transfer mode filters out wait and idle states , providing an easier to read display. Timing mode timing analysis is supported up to 500 MHz. Channel-to-channel skew is 1 ns. The preprocessor allows you to improve trace readability by controlling the amount of information being sent to the analyzer. For example, you can configure the preprocessor to filter out cache invalidation cycles from the analyzer. For DMA transfers you can configure the preprocessor to send all DMA cycles, to send just one cycle which indicates a DMA transfer occurred, or to send no DMA cycles to the analyzer. The following types of instructions can be selected to be displayed or suppressed: unexecuted prefetches, jumps, calls/returns, and other instructions. In addition, the following operations can be displayed or suppressed: memory read/writes, I/O read/writes, special cycles, and interrupt acknowledge cycles. Also, FPU instructions are decoded in the display.

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